VEGA Signal Converters
Micram VEGA DAC/ADC chips are the only products of their kind providing real-time, streaming, unbuffered data conversion with flexible sampling rates of up to and above 30GS/s. VEGAenables the only practical, running 100G data transmission development environment available today. VEGA give 100GbE developers the power to make immediate, significant progress by providing an off-the-shelf, full-bandwidth 100G environment – without a custom chip run. VEGA is open, scalable and easily adapted to any application-specific requirements.
Unlike other DAC/ADC product architectures which force early design decisions that are costly and time-consuming to change, VEGA enables developers to rapidly prototype their ideas, test them and make revisions on the fly. With VEGA, developers can quickly assemble a highly productive, real-time 100G development system and start creating system-level product designs immediately.
DAC 2 and DAC 3
The Low Risk Path for 100GbE Development
Evaluation board usable with both ADC and DAC Includes microcontroller with USB interface for testing w/o FPGA Most circuitry is located on the back side of the evaluation board Test Setup with FPGA Front: Evaluation Board with DAC module Back: Xilinx ML424 Board with Virtex4-FX140 (24 RocketIOs) 15 GHz clock is fed to the DAC module (blue cable) Reference clock (:40) for FPGA is generated by DAC 48 RF-cables for 24 differential SerDes links...read more
VEGA ADC 30 Key Data The ADC 30 is designed for 30GS/s to show the inherent performance and functional capability of the VEGA modular approach. It consists of an input-amplifier, track-and-hold circuit, ADC-core and output logic. The converter has a bandwidth of 20GHz, which shows up when operating two ADCs in interleave mode to provide 60GS/s @ 20 GHz. Like DAC II, the ADC30s are available with an evaluation board. The ADC chip is mounted to the PCB board on a chip-carrier (shown here) which allows easy swapping of ADC chips to different (customer) boards. The conversion will be interleaved, there will be several blocks sharing the conversion operation. Results are processed in a logic block and de-mulitplexed for further processing by external CMOS FPGA chips. The RF-Clock is fed directly into the A/D converter and provides a reference clock to the FPGA. Depending on customer needs there is an option to include a VCO on the chip in later versions. Data-transfer to FPGA will be via 24 serial lines (LVDS or PCML, differential) running at fsample/4, e.g. 7.5Gb/s for 30GS/s (6 bit * 1:4 Mux –> 24 signals). The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and signal input are interfaced by K-connectors. In addition a register bus (LVTTL, serial) is used to configure and calibrate the A/D converter. Dedicated on-chip circuitry will support for easy calibration. The high-speed interface will carry raw data only, without line coding (except scrambling) or framing. To compensate for skew on PCB as well as to align input stages in the FPGA, the A/D converter can be switched into a dedicated synchronization mode. Since some FPGA require a certain amount of data edges on the input channels to stay synchronized, the data transmitted to the FPGA can be optionally PRBS scrambled to enforce transitions even while the ADC-input is static. ADC 30 block diagramm TARGET DATA Sampling Rate Single chip 30GS/sDual chip 60GS/s Physical Resolution 6 bits ENOB >4.5 bits @ 14 GHz Bandwidth (-3db) 20 GHz Input range (full scale) 400 mVpp VEGA ADC30 datasheet: 030_VEGA ADC30...read more
CD17 17 GHz Versatile Clock Distribution Module The CD17 is a versatile clock distribution module for clock signals up to 17 GHz. Key features are: single-ended and differential IO operation, programmable reference clock divider, synchronous clock start/stop, broadband operation, adjustable main clock output swing and delay, single supply voltage, PLL, crystal oscillator and 17 GHz VCO. Main purpose of the CD17 is driving and synchronizing multiple multiplexers, ADCs or DACs. The symmetrical clock input buffer allows for single ended as well as differential drive. Additional pins aim for offset measurement and adjustment.Two main clock output buffers can be adjusted from 0.3 to 1.2V single-ended swing and can be used either single-ended or differential. The phase of the main clock can be controlled in a 95 ps range. For synchronizing multiple chips, the main clock can be switched to static low and restarted synchronously. To provide clocks for FPGAs, a programmable reference divider (ratio 1:2 up to 1:896) with two differential output buffers is included. Finally, for using either the build in LC-tank VCO or controlling external VCO, a PLL with a fixed divide-by-512 ratio and a crystal oscillator buffer is built-in. Main fields of application are Clock distribution and Synchronization of multiple ADCs, DACs, MUX. Electrical data Parameter Min. Typ. Max. Unit Power supply -3.3 V Current consumption 460 mA Clockrate 1 17 18 GHz VCO tuning range 14.5 18 GHz Output amplitude 1.2SE 2.4diff V CD 17 datasheet:...read more
DAC I and DAC II We are now offering two versions of our second-generation VEGA DAC: DAC I with sampling rates up to 25 GS/s, and DAC II which achieves rates as high as 34GS/s. The VEGA DAC digital-to-analog signal converter family, with a sample rate of up to 34GS/s at 20GHz bandwidth. Incorporating everything we’ve learned from the success of the sold-out VEGA DAC25, our latest chip delivers extraordinary performance that meets – and even exceeds – the capabilities of the latest generation of FPGAs, including the Xilinx VIRTEX-5, VIRTEX-6 and Altera Stratix IV. Up to 4 DAC chips can be synchronized with our CD15 timing module for even greater performance potential. The scalable open architecture offers a high degree of flexibility in order to adopt the rapidly changing requirements in future high-speed converter applications. Having a physical resolution of 6 bits, we measured an ENOB of >4 bit at 30 GS/s for sinusoidal differential signals up to 5 GHz. In the high-speed front end, the VEGA architecture allows a tradeoff between conversion rate, resolution and power consumption for optimum tailored application specific performance. For massive signal and data processing in digital domain, the architecture offers a parallel interface to either commercially available high-speed FPGAs or to a separate custom specific realization in off the shelf standard CMOS technology. This allows to keep the high performance analog front end, and to implement the latest developments in data/signal processing by updates on the CMOS part only. The chip with 6 bit resolution is available now. It comes along with an application board that offers two different input interfaces. A low speed USB or RS232 interface to a PC allows configuring and loading up repeatable test-patterns to the converter. For continuous at-speed input, a high-speed interface offers 24 differential inputs for drive with commercially available FPGAs, e.g. Xilinx VIRTEX-5, VIRTEX-6 or Altera Stratix V. The converter is well suited for direct digital synthesis of ultra high-speed arbitrary waveforms e.g. for advanced 100 Gbit Ethernet transmission schemes. The data transfer from FPGA/CMOS is carried via 24 serial lines (LVDS) running at fsample/4, i.e. 8.5Gb/s for 34GS/s (6 bit * 1:4 Mux ==> 24 signals). The FPGA interface carries raw data only, i.e. no line coding etc. but optionally can be PRBS scrambled. In addition, a register bus (LVTTL, serial) can be used to configure the D/A converter. The Evaluation Board (shown here) comes with a microcontroller and a software application to control operation modes. It is able to check the synchronization of the 24 FPGA channels. The 24 differential serial data lines are connected with the chip carrier module via high density Samtec RF connectors. All other DC signals are also carried through Samtec connectors. Clock input and DAC output are interfaced by K-connectors. SPECIFICATION DATA Parameter Min. Typ. Max. Unit Junction temperature range 0 125 °C Ambient temperature range 0 50 °C Power supply (4 voltages) +3.0 +1.3 -3.0 -4.3 +3.3 +1.5 -3.3 -4.5 +3.6 +1.7 -3,6 -4.7 V V V V Power dissipation 13 W Conversion rate 0 30 34 GS/s Analog bandwidth >18 GHz Resolution (physical) 6 bit ENOB* @ 30GS/s0…1 GHz1…5 GHz5…10 GHz10…14 GHz >5.0>4.0>3.5>3.0 bit Output amplitude**, se, fs 0 800 mv * for differential sinusodial signals ** se = single-ended, fs = full-scale (e.g. 6b000000...read more